Ing. Jiří Jeníček, Ph.D.

Ing. Jiří Jeníček, Ph.D.
Institute of Information Technology and Electronics (ITE): Academic staff

E-mail:: jiri.jenicek@tul.cz
Office:: A02029
Tel.:: +420 48535 3021
STAG:: STAG profile

Consulting Hours

upon request

Specialisation

test vector compression
parallel computing
computer graphics

Achieved education

2005 Ing.
2009 Ph.D.

Other appointments

(Older publications: here )

Publications

ROZKOVEC, M., PALEČEK, K. , and JENÍČEK, J. OPC UA QS pro kamerový sensor [software].
ROZKOVEC, M., PALEČEK, K., JENÍČEK, J. , and ČEVONA, P. Prototyp zařízení pro analýzu cizích příměsí a nečistot ve zpracovávaném materiálu čisticího a mykacího stroje. [funkční vzorek]
JAKUBÍK, T. , and JENÍČEK, J. Feasibility of OFDM and FHSS in a Single Home Automation and Security Network 2020 43rd International Conference on Telecommunications and Signal Processing (TSP) 1. ed. IEEE, 2020 P. 19 – 22. ISBN: 978-1-72816-376-5.
JAKUBÍK, T. , and JENÍČEK, J. SDR All-channels Receiver for FHSS Sensor Network in Cortex-M 2019 42nd International Conference on Telecommunications and Signal Processing (TSP) 1. ed. IEEE, 2019 P. 32 – 35. ISBN: 978-1-72811-864-2.
JAKUBÍK, T. , and JENÍČEK, J. Mnohokanálový softwarový FHSS přijímač na Cortex-M Počítačové architektury a diagnostika PAD 2018 Plzeň: , 2018 P. 29 – 32. ISBN: 978-80-261-0814-6.
všechny publikace
JAKUBÍK, T. , and JENÍČEK, J. SDR All-channels Receiver for FHSS Sensor Network International Conference on Applied Electronics 1. ed. Plzeň: IEEE, 2018 P. neuvedeny (4 stranky). ISBN: 978-802610721-7, ISSN: 1803-7232.
JAKUBÍK, T. , and JENÍČEK, J. Asymmetric Low-power FHSS Algorithm Electronics, Control, Measurement, Signals and their Application to Mechatronics (ECMSM), 2017 IEEE International Workshop of Donostia-San Sebastian, Spain: IEEE, 2017 P. 309 – 314. ISBN: 978-1-5090-5582-1.
JAKUBÍK, T. , and JENÍČEK, J. OFDM and FHSS Hybrid Network Počítačové architektúry & diagnostika PAD 2017 Smolenice, Slovakia: , 2017 P. 16 – 19. ISBN: 978-80-972784-0-3.
NOVÁK, O., ROZKOVEC, M. , and JENÍČEK, J. Sequential Test Decompressors with Fast Tester Bits Wide-Spreading JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS SINGAPORE: WORLD SCIENTIFIC PUBL CO PTE LTD, 5 TOH TUCK LINK, SINGAPORE 596224, 2017, vol. 26, issue 8. P. neuvedeny (16 stran). ISSN: 0218-1266.
NOVÁK, O., JENÍČEK, J. , and ROZKOVEC, M. Sequential test decompressors with fast variable wide spreading Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016 Košice, Slovakia: IEEE, 2016 P. 132 – 137. ISBN: 978-1-5090-2816-0.
NOVÁK, O., JENÍČEK, J. , and ROZKOVEC, M. Test Decompressor Effectivity Improvement Proceedings - 19th Euromicro Conference on Digital System Design, DSD 2016 Limassol, Cyprus: IEEE, 2016 P. 661 – 664. ISBN: 978-1-5090-2816-0.
ROZKOVEC, M. , and JENÍČEK, J. Implementace algortimů konvolučních filtrů do FPGA - spuštění webového portálu podpory projektu (2014V003), 2015
NOVÁK, O., JENÍČEK, J. , and ROZKOVEC, M. LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015 1. ed. Belgrade, Serbia: Institute of Electrical and Electronics Engineers Inc., 2015 P. 9 – 14. ISBN: 978-1-4799-6780-3.
NOVÁK, O., JENÍČEK, J. , and ROZKOVEC, M. Test compression for circuits with multiple scan chains 2015 16th Latin-American Test Symposium, LATS 2015 1. ed. Puerto Vallarta; Mexico: Institute of Electrical and Electronics Engineers, 2015 P. neuvedeno. ISBN: 978-1-4673-6710-3.

Topics of Student work

Ceph cluster - Software Defined Storage, ITE, 2024
Floating license monitor, ITE, 2024
FPGA Implementation of RISC-V Core, ITE, 2023
Procedural generation of 2D map, ITE, 2023

Správa studentských prací a projektů

Show all staff Co-workers at ITE

Ing. Jiří Jeníček, Ph.D.

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